The present disclosure relates to computing timing constraint sensitivities of circuit models based upon actual test probability measurements and using the timing constraint sensitivities to verify characterized circuit model sensitivities that were generated during library characterization.
Integrated circuit design involves the creation of electronic components, such as transistors, resistors, capacitors and the metallic interconnect of these components onto a piece of a semiconductor, such as silicon. A typical standard cell based integrated circuit design cycle involves multiple stages such as system specification, architectural design, functional/logic design, static timing analysis, physical design, timing optimization, and fabrication.
Integrated circuit wafer fabrication facilities adhere to strict standards in each stage of producing integrated circuits. Even with the strict standards, slight variations occur between wafer lots, wafers within a lot, dies within a wafer, and within a die. Transistor variation within a die is referred to as across chip variation (ACV) which can be systematic (correlated), where each transistor has the same random variation, or random (uncorrelated) where each transistor has its own unique random variation. Random ACV may be caused by variations in impurity concentration densities, oxide thicknesses, diffusion depths, etc.
Accurate timing constraint modeling (setup, hold, pulse width) for sequential elements (latches, flip flops, etc.) is essential for designing high performance circuits. A typical sequential circuit may consist of several transistors each of which has properties such as length, width and threshold voltage that, due to random ACV, can vary independently from transistor to transistor. Timing constraints are sensitive to these variations that, in turn, cause uncertainty in circuit behavior and must be accounted for and characterized as timing constraint sensitivities. Timing constraints, and timing constraint sensitivities to ACV, are key inputs to Statistical Static Timing Analysis (SSTA) tools for a successful integrated circuit design.